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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
Quad SPI-3 to SPI-4 Bridge Application Overview
The SPI-3 interface (referred to interchangeably as PL-3 or POS-PHY Level 3) is designed to comply with the OIF
implementation agreement (OIF-SPI3-01.0). The bridge design implements an SPI-3 LINK layer. The primary appli-
cation is to bridge a network processor with an SPI-4 interface to multiple 2.5Gb framers, each with an SPI-3 inter-
face as shown in Figure 1.
Figure 1. Application of Quad SPI-3 to SPI-4 Bridge
Line Card
ORSPI4
2.5G Optical
I/F
2.5G
Framer
SPI-3
Link Layer
0
2.5G Optical
I/F
2.5G Optical
I/F
2.5G Optical
I/F
2.5G
Framer
2.5G
Framer
2.5G
Framer
SPI-3
Link Layer
1
SPI-3
Link Layer
2
SPI-3
Link Layer
3
SPI-4
Network
Processor
Element
(NPE)
Functional Description
Figure 2. SPI-3 to SPI-4 Link Layer Bridge Solution Simpli?ed Block Diagram
Embedded ASB Section
SPIA_TX32CLKx
IP in FPGA Section
RFCLK
RVAL
Tx_D[38:0]
WD_CNT_RST
SPI-3
Receive
RENB
RDAT[31:0]
Tx
DPRAM
Port
Tx_WE
Tx_Port[7:0]
Tx_A[2:0]
FIFO_FULL
ATREF_CLK
Tx_PortID[7:0]
Interface
and
DPRAM
Write
Control
Polling
Sequence
RMOD[1:0]
RPRTY
REOP
RSOP
RERR
RSX
TADR[2:0]
Write
Sequence
Tx_Bkp
Tx_Stat[1:0]
No connect
Controller
Logic
SPIA_RX32_CLKx
Polling
Satus
Table
PTPA
DTPA[7:0]
STPA
Rx
DPRAM
Rx_D[39:0]
Rx_FIFO_Empty
Rx_A[2:0]
Rx_RE
SPI-3
Transmit
Interface
TFCLK
TENB
TDAT[31:0]
TMOD[1:0]
and
0
DPRAM
Read
TPRTY
TSOP
Rx
Port
Status
Sequencer
Rx_Ext_Status_enable
Rx_Port_Status[1:0]
Rx_FPGA_Port_ID[7:0]
Rx_PSS_WE
No connect
Control
TEOP
TERR
TSX
Note: SPI-3 interface logic can be replicated up to 4x (quad) for 10G applications.
3
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